IMR=B_0x0, VBR=B_0x0
LTDC shadow reload configuration register
| IMR | immediate reload This bit is set by software and cleared only by hardware after reload. 0 (B_0x0): no effect 1 (B_0x1): The shadow registers are reloaded immediately. |
| VBR | vertical blanking reload This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set). 0 (B_0x0): no effect 1 (B_0x1): The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). |