stm32 /stm32h7rs /STM32H7R /OTG_HS /OTG_DOEPCTL0

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Interpret as OTG_DOEPCTL0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)MPSIZ 0 (USBAEP)USBAEP 0 (B_0x0)NAKSTS 0EPTYP 0 (SNPM)SNPM 0 (STALL)STALL 0 (CNAK)CNAK 0 (SNAK)SNAK 0 (EPDIS)EPDIS 0 (EPENA)EPENA

NAKSTS=B_0x0, MPSIZ=B_0x0

Description

OTG device control OUT endpoint 0 control register

Fields

MPSIZ

Maximum packet size The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN endpoint 0.

0 (B_0x0): 64 bytes

1 (B_0x1): 32 bytes

2 (B_0x2): 16 bytes

3 (B_0x3): 8 bytes

USBAEP

USB active endpoint This bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces.

NAKSTS

NAK status Indicates the following: When either the application or the core sets this bit, the core stops receiving data, even if there is space in the Rx FIFO to accommodate the incoming packet. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake.

0 (B_0x0): The core is transmitting non-NAK handshakes based on the FIFO status.

1 (B_0x1): The core is transmitting NAK handshakes on this endpoint.

EPTYP

Endpoint type Hardcoded to 00 for control.

SNPM

Snoop mode This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory.

STALL

STALL handshake The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bits setting, the core always responds to SETUP data packets with an ACK handshake.

CNAK

Clear NAK A write to this bit clears the NAK bit for the endpoint.

SNAK

Set NAK A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit on a transfer completed interrupt, or after a SETUP is received on the endpoint.

EPDIS

Endpoint disable The application cannot disable control OUT endpoint 0.

EPENA

Endpoint enable The application sets this bit to start transmitting data on endpoint 0. The core clears this bit before setting any of the following interrupts on this endpoint: SETUP phase done Endpoint disabled Transfer completed

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