DMAEN=B_0x0, TXFELVL=B_0x0_DEVICE_MODE, GINTMSK=B_0x0, PTXFELVL=B_0x0
OTG AHB configuration register
| GINTMSK | Global interrupt mask The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bits setting, the interrupt status registers are updated by the core. Note: Accessible in both device and host modes. 0 (B_0x0): Mask the interrupt assertion to the application. 1 (B_0x1): Unmask the interrupt assertion to the application. |
| HBSTLEN | Burst length/type 0000 Single: Bus transactions use single 32 bit accesses (not recommended) 0001 INCR: Bus transactions use unspecified length accesses (not recommended, uses the INCR AHB bus command) 0011 INCR4: Bus transactions target 4x 32 bit accesses 0101 INCR8: Bus transactions target 8x 32 bit accesses 0111 INCR16: Bus transactions based on 16x 32 bit accesses Others: Reserved |
| DMAEN | DMA enabled 0 (B_0x0): The core operates in slave mode 1 (B_0x1): The core operates in DMA mode |
| TXFELVL | Tx FIFO empty level This bit indicates when IN endpoint Transmit FIFO empty interrupt (TXFE in OTG_DIEPINTx) is triggered: This bit indicates when the nonperiodic Tx FIFO empty interrupt (NPTXFE bit in OTG_GINTSTS) is triggered: 0 (B_0x0_DEVICE_MODE): The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is half empty 1 (B_0x1_DEVICE_MODE): The TXFE (in OTG_DIEPINTx) interrupt indicates that the IN endpoint Tx FIFO is completely empty |
| PTXFELVL | Periodic Tx FIFO empty level Indicates when the periodic Tx FIFO empty interrupt bit in the OTG_GINTSTS register (PTXFE bit in OTG_GINTSTS) is triggered. Note: Only accessible in host mode. 0 (B_0x0): PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is half empty 1 (B_0x1): PTXFE (in OTG_GINTSTS) interrupt indicates that the Periodic Tx FIFO is completely empty |