stm32 /stm32h7rs /STM32H7R /OTG_HS /OTG_GRXSTSR_DEVICE

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Interpret as OTG_GRXSTSR_DEVICE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0EPNUM0BCNT0 (B_0x0)DPID 0PKTSTS0FRMNUM0 (STSPHST)STSPHST

DPID=B_0x0

Description

OTG receive status debug read register

Fields

EPNUM

Endpoint number Indicates the endpoint number to which the current received packet belongs.

BCNT

Byte count Indicates the byte count of the received data packet.

DPID

Data PID Indicates the data PID of the received OUT data packet

0 (B_0x0): DATA0

1 (B_0x1): DATA2

2 (B_0x2): DATA1

3 (B_0x3): MDATA

PKTSTS

Packet status Indicates the status of the received packet Others: Reserved

1 (B_0x1): Global OUT NAK (triggers an interrupt)

2 (B_0x2): OUT data packet received

3 (B_0x3): OUT transfer completed (triggers an interrupt)

4 (B_0x4): SETUP transaction completed (triggers an interrupt)

6 (B_0x6): SETUP data packet received

FRMNUM

Frame number This is the least significant 4 bits of the frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported.

STSPHST

Status phase start Indicates the start of the status phase for a control write transfer. This bit is set along with the OUT transfer completed PKTSTS pattern.

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