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stm32 /stm32h7rs /STM32H7R /OTG_HS /OTG_HAINT

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Interpret as OTG_HAINT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0HAINT

Description

OTG host all channels interrupt register

Fields

HAINT

Channel interrupts One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32