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stm32 /stm32h7rs /STM32H7R /OTG_HS /OTG_HAINTMSK

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Interpret as OTG_HAINTMSK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HAINTM

HAINTM=B_0x0

Description

OTG host all channels interrupt mask register

Fields

HAINTM

Channel interrupt mask One bit per channel: Bit 0 for channel 0, bit 15 for channel 15

0 (B_0x0): Masked interrupt

1 (B_0x1): Unmasked interrupt

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32