FSLSPCS=B_0x0_LS_HOST_MODE
OTG host configuration register
| FSLSPCS | FS/LS PHY clock select Others: Reserved Note: The FSLSPCS must be set on a connection event according to the speed of the connected device (after changing this bit, a software reset must be performed). 0 (B_0x0_LS_HOST_MODE): FIELD Reserved 1 (B_0x1_FS_HOST_MODE): PHY clock is running at 48 MHz 2 (B_0x2_LS_HOST_MODE): Select 6 MHz PHY clock frequency 3 (B_0x3_LS_HOST_MODE): FIELD Reserved |
| FSLSS | FS- and LS-only support The application uses this bit to control the cores enumeration speed. Using this bit, the application can make the core enumerate as an FS host, even if the connected device supports HS traffic. Do not make changes to this field after initial programming. |