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stm32 /stm32h7rs /STM32H7R /OTG_HS /OTG_HPTXSTS

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Interpret as OTG_HPTXSTS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PTXFSAVL0 (B_0x0)PTXQSAV0PTXQTOP

PTXQSAV=B_0x0, PTXFSAVL=B_0x0

Description

OTG_Host periodic transmit FIFO/queue status register

Fields

PTXFSAVL

Periodic transmit data FIFO space available Indicates the number of free locations available to be written to in the periodic Tx FIFO. Values are in terms of 32-bit words n: n words available (where 0 UNDER OR EQUAL n UNDER OR EQUAL PTXFD) Others: Reserved

0 (B_0x0): Periodic Tx FIFO is full

1 (B_0x1): 1 word available
PTXQSAV

Periodic transmit request queue space available Indicates the number of free locations available to be written in the periodic transmit request queue. This queue holds both IN and OUT requests. n: n locations available (0 UNDER OR EQUAL n UNDER OR EQUAL 8) Others: Reserved

0 (B_0x0): Periodic transmit request queue is full

1 (B_0x1): 1 location available
PTXQTOP

Top of the periodic transmit request queue This indicates the entry in the periodic Tx request queue that is currently being processed by the MAC. This register is used for debugging. Bit 31: Odd/Even frame 0XXXXXXX: send in even frame 1XXXXXXX: send in odd frame Bits 30:27: Channel/endpoint number Bits 26:25: Type XXXXX00X: IN/OUT XXXXX01X: Zero-length packet XXXXX11X: Disable channel command Bit 24: Terminate (last entry for the selected channel/endpoint)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32