BOOSTE=B_0x0, AVDEN=B_0x0, RLPSN=B_0x0, FLPS=B_0x0, DBP=B_0x0, PVDE=B_0x0, AVDREADY=B_0x0, ALS=B_0x0, SVOS=B_0x0, PLS=B_0x0
PWR control register 1
| SVOS | System Stop mode voltage scaling selection. 0 (B_0x0): SVOS Low 1 (B_0x1): SVOS High (default) |
| PVDE | Programmable voltage detector enable 0 (B_0x0): Programmable voltage detector disabled. 1 (B_0x1): Programmable voltage detector enabled |
| PLS | Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. 0 (B_0x0): PVD level 1 1 (B_0x1): PVD level 2 2 (B_0x2): PVD level 3 3 (B_0x3): PVD level 4 4 (B_0x4): PVD level 5 5 (B_0x5): PVD level 6 6 (B_0x6): PVD level 7 7 (B_0x7): External voltage level on PVD_IN pin, compared to internal VREFINT level. |
| DBP | Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in the PWR_CSR1 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. 0 (B_0x0): Access to RTC, RTC backup registers and backup SRAM disabled 1 (B_0x1): Access to RTC, RTC backup registers and backup SRAM enabled |
| FLPS | Flash low-power mode in Stop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when device is in Stop mode. consumption). 0 (B_0x0): Flash memory remains in normal mode when device enters Stop (quick restart time). 1 (B_0x1): Flash memory enters low-power mode when device enters Stop mode (low-power |
| RLPSN | RAM low power mode disable in STOP. When set the RAMs will not enter to low power mode when the system enters to STOP. 0 (B_0x0): RAM enters to low power mode when system enters to STOP. 1 (B_0x1): RAM remains in normal mode when system enters to STOP. |
| BOOSTE | analog switch VBoost control This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits. 0 (B_0x0): booster disabled (default) 1 (B_0x1): booster enabled if analog voltage ready (AVD_READY = 1) |
| AVDREADY | analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected VDDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_CSR1 register) after setting the AVDEN bit and selecting the supply level to be monitored (ALS bits). 0 (B_0x0): peripheral analog voltage VDDA not ready (default) 1 (B_0x1): peripheral analog voltage VDDA ready |
| AVDEN | Peripheral voltage monitor on VDDA enable 0 (B_0x0): Peripheral voltage monitor on VDDA disabled 1 (B_0x1): Peripheral voltage monitor on VDDA enabled |
| ALS | Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details. 0 (B_0x0): AVD level 1 1 (B_0x1): AVD level 2 2 (B_0x2): AVD level 3 3 (B_0x3): AVD level 4 |