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stm32 /stm32h7rs /STM32H7R /PWR /PWR_CSR3

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Interpret as PWR_CSR3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PDDS 0 (B_0x0)CSSF 0 (B_0x0)STOPF 0 (B_0x0)SBF

CSSF=B_0x0, PDDS=B_0x0, STOPF=B_0x0, SBF=B_0x0

Description

PWR CPU control register 3

Fields

PDDS

Power Down Deepsleep. This bit allows CPU to define the Deepsleep mode

0 (B_0x0): Stop mode when device enters Deepsleep.

1 (B_0x1): Standby mode when device enters Deepsleep.
CSSF

Clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware.

0 (B_0x0): No effect.

1 (B_0x1): flags (STOPF, SBF) are cleared.
STOPF

STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU CSSF bit.

0 (B_0x0): System has not been in Stop mode

1 (B_0x1): System has been in Stop mode
SBF

System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU CSSF bit

0 (B_0x0): System has not been in Standby mode

1 (B_0x1): System has been in Standby mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32