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stm32 /stm32h7rs /STM32H7R /PWR /PWR_PDR1

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Interpret as PWR_PDR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)UNLOCKED 0 (B_0x0)SDFPWMEN 0 (B_0x0)SYNC_ADC

UNLOCKED=B_0x0, SYNC_ADC=B_0x0, SDFPWMEN=B_0x0

Description

PWR debug register 1

Fields

UNLOCKED

Debug Register Unlocked.

0 (B_0x0): accessed locked: key was not written and after each register write access.

1 (B_0x1): after key 0xCAFECAFE was written in this register
SDFPWMEN

Step down converter force PWM mode

0 (B_0x0): SD_Converter Normal mode

1 (B_0x1): SD_Converter forced PWM mode
SYNC_ADC

(Non-User bit)

0 (B_0x0): SD_Converter clock free running

1 (B_0x1): SD_Converter clock synchronised to ADC.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32