RAMECC_M5SR

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Interpret as RAMECC_M5SR

DEDF=B_0x0, DEBWDF=B_0x0, SEDCF=B_0x0

RAMECC monitor 5 status register

SEDCF	ECC single error detected and corrected flag This bit is set by hardware. It is cleared by software by writing a 0 0 (B_0x0): no error detected and corrected 1 (B_0x1): error detected and corrected
DEDF	ECC double error detected flag This bit is set by hardware. It is cleared by software by writing a 0 0 (B_0x0): no error detected 1 (B_0x1): error detected
DEBWDF	ECC double error on byte write (BW) detected flag This bit is set by hardware. It is cleared by software by writing a 0 0 (B_0x0): no error detected 1 (B_0x1): error detected

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