OTGHSEN=B_0x0, GPDMA1EN=B_0x0, ADC12EN=B_0x0, ETH1RXEN=B_0x0, ETH1MACEN=B_0x0, USBPHYCEN=B_0x0, ADFEN=B_0x0, ETH1TXEN=B_0x0, OTGFSEN=B_0x0
RCC AHB1 clock enable register
| GPDMA1EN | GPDMA1 clock enable Set and reset by software. 0 (B_0x0): GPDMA1 clock disabled (default after reset) 1 (B_0x1): GPDMA1 clock enabled |
| ADC12EN | ADC1 and 2 peripheral clocks enable Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the hclk1 bus interface clock. 0 (B_0x0): ADC1 and 2 peripheral clocks disabled (default after reset) 1 (B_0x1): ADC1 and 2 peripheral clocks enabled |
| ETH1MACEN | ETH1 MAC peripheral clock enable Set and reset by software. 0 (B_0x0): ETH1 MAC peripheral clock disabled (default after reset) 1 (B_0x1): ETH1 MAC peripheral clock enabled |
| ETH1TXEN | ETH1 transmission clock enable Set and reset by software. 0 (B_0x0): ETH1 transmission clock disabled (default after reset) 1 (B_0x1): ETH1 transmission clock enabled |
| ETH1RXEN | ETH1 reception clock enable Set and reset by software. 0 (B_0x0): ETH1 reception clock disabled (default after reset) 1 (B_0x1): ETH1 reception clock enabled |
| OTGHSEN | OTGHS clocks enable Set and reset by software. 0 (B_0x0): OTGHS clocks disabled (default after reset) 1 (B_0x1): OTGHS clocks enabled |
| USBPHYCEN | USBPHYC clocks enable Set and reset by software. 0 (B_0x0): USBPHYC clocks disabled (default after reset) 1 (B_0x1): USBPHYC clocks enabled |
| OTGFSEN | OTGFS peripheral clocks enable Set and reset by software. 0 (B_0x0): OTGFS peripheral clocks disabled (default after reset) 1 (B_0x1): OTGFS peripheral clocks enabled |
| ADFEN | ADF clocks enable Set and reset by software. 0 (B_0x0): ADF clocks disabled (default after reset) 1 (B_0x1): ADF clocks enabled |