SRAM1EN=B_0x0, SDMMC2EN=B_0x0, PSSIEN=B_0x0, CORDICEN=B_0x0, SRAM2EN=B_0x0
RCC AHB2 clock enable register
| PSSIEN | PSSI peripheral clocks enable Set and reset by software. 0 (B_0x0): PSSI peripheral clocks disabled (default after reset) 1 (B_0x1): PSSI peripheral clocks enabled: |
| SDMMC2EN | SDMMC2 and SDMMC2 delay clock enable Set and reset by software. 0 (B_0x0): SDMMC2 and SDMMC2 delay clock disabled (default after reset) 1 (B_0x1): SDMMC2 and SDMMC2 delay clock enabled |
| CORDICEN | CORDIC clock enable Set and reset by software. 0 (B_0x0): CORDIC clock disabled (default after reset) 1 (B_0x1): CORDIC clock enabled |
| SRAM1EN | SRAM1 clock enable Set and reset by software. 0 (B_0x0): SRAM1 clock disabled (default after reset) 1 (B_0x1): SRAM1 clock enabled |
| SRAM2EN | SRAM2 clock enable Set and reset by software. 0 (B_0x0): SRAM2 clock disabled (default after reset) 1 (B_0x1): SRAM2 clock enabled |