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stm32 /stm32h7rs /STM32H7R /RCC /RCC_AHB2RSTR

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Interpret as RCC_AHB2RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PSSIRST 0 (B_0x0)SDMMC2RST 0 (B_0x0)CORDICRST

CORDICRST=B_0x0, SDMMC2RST=B_0x0, PSSIRST=B_0x0

Description

RCC AHB2 peripheral reset register

Fields

PSSIRST

PSSI block reset Set and reset by software.

0 (B_0x0): does not reset PSSI block (default after reset)

1 (B_0x1): resets PSSI block
SDMMC2RST

SDMMC2 and SDMMC2 delay blocks reset Set and reset by software.

0 (B_0x0): does not reset SDMMC2 and SDMMC2 delay blocks (default after reset)

1 (B_0x1): resets SDMMC2 and SDMMC2 delay blocks
CORDICRST

CORDIC reset Set and reset by software.

0 (B_0x0): does not reset CORDIC block (default after reset)

1 (B_0x1): resets CORDIC block

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32