SDMMC1EN=B_0x0, GFXMMUEN=B_0x0, GPUEN=B_0x0, IOMNGREN=B_0x0, XSPI2EN=B_0x0, XSPI1EN=B_0x0, FMCEN=B_0x0, DMA2DEN=B_0x0, JPEGEN=B_0x0, HPDMA1EN=B_0x0
RCC AHB5 clock enable register
| HPDMA1EN | HPDMA1 peripheral clock enable Set and reset by software. 0 (B_0x0): HPDMA1 peripheral clock disabled (default after reset) 1 (B_0x1): HPDMA1 peripheral clock enabled |
| DMA2DEN | DMA2D peripheral clock enable Set and reset by software. 0 (B_0x0): DMA2D peripheral clock disabled (default after reset) 1 (B_0x1): DMA2D peripheral clock enabled |
| JPEGEN | JPEG peripheral clock enable Set and reset by software. 0 (B_0x0): JPEG peripheral clock disabled (default after reset) 1 (B_0x1): JPEG peripheral clock enabled |
| FMCEN | FMC and MCE3 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock. 0 (B_0x0): FMC and MCE3 peripheral clocks disabled (default after reset) 1 (B_0x1): FMC and MCE3 peripheral clocks enabled |
| XSPI1EN | XSPI1 and MCE1 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 0 (B_0x0): XSPI1 and MCE1 peripheral clocks disabled (default after reset) 1 (B_0x1): XSPI1 and MCE1 peripheral clocks enabled |
| SDMMC1EN | SDMMC1 and DB_SDMMC1 peripheral clocks enable Set and reset by software. 0 (B_0x0): SDMMC1 and DB_SDMMC1 peripheral clocks disabled (default after reset) 1 (B_0x1): SDMMC1 and DB_SDMMC1 peripheral clocks enabled |
| XSPI2EN | XSPI2 and MCE2 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 0 (B_0x0): XSPI2 and MCE2 peripheral clocks disabled (default after reset) 1 (B_0x1): XSPI2 and MCE2 peripheral clocks enabled |
| IOMNGREN | XSPIM peripheral clock enable Set and reset by software. 0 (B_0x0): XSPIM peripheral clock disabled (default after reset) 1 (B_0x1): XSPIM peripheral clock enabled |
| GFXMMUEN | GFXMMU peripheral clock enable Set and reset by software. 0 (B_0x0): GFXMMU peripheral clock disabled (default after reset) 1 (B_0x1): GFXMMU peripheral clock enabled |
| GPUEN | GPU peripheral clock enable Set and reset by software. 0 (B_0x0): GPU peripheral clock disabled (default after reset) 1 (B_0x1): GPU peripheral clock enabled |