RCC_AHB5RSTR

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Interpret as RCC_AHB5RSTR

JPEGRST=B_0x0, XSPI2RST=B_0x0, FMCRST=B_0x0, HPDMA1RST=B_0x0, GPURST=B_0x0, SDMMC1RST=B_0x0, IOMNGRRST=B_0x0, DMA2DRST=B_0x0, XSPI1RST=B_0x0, GFXMMURST=B_0x0

Description

RCC AHB5 peripheral reset register

Fields

HPDMA1RST	HPDMA1 block reset Set and reset by software. 0 (B_0x0): reset is released (default after reset) 1 (B_0x1): reset is asserted
DMA2DRST	DMA2D block reset Set and reset by software. 0 (B_0x0): reset is released (default after reset) 1 (B_0x1): reset is asserted
JPEGRST	JPEG block reset Set and reset by software. 0 (B_0x0): reset is released (default after reset) 1 (B_0x1): reset is asserted
FMCRST	FMC and MCE3 blocks reset Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. 0 (B_0x0): reset is released (default after reset) 1 (B_0x1): reset is asserted
XSPI1RST	XSPI1 and MCE1 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 0 (B_0x0): reset is released (default after reset) 1 (B_0x1): reset is asserted
SDMMC1RST	SDMMC1 and DB_SDMMC1 blocks reset Set and reset by software. 0 (B_0x0): reset is released (default after reset) 1 (B_0x1): reset is asserted
XSPI2RST	XSPI2 and MCE2 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. 0 (B_0x0): reset is released (default after reset) 1 (B_0x1): reset is asserted
IOMNGRRST	XSPIM reset Set and reset by software. 0 (B_0x0): reset is released (default after reset) 1 (B_0x1): reset is asserted
GFXMMURST	GFXMMU block reset Set and reset by software. 0 (B_0x0): reset is released (default after reset) 1 (B_0x1): reset is asserted
GPURST	GPU block reset Set and reset by software. 0 (B_0x0): reset is released (default after reset) 1 (B_0x1): reset is asserted

Links

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