CKPERSEL=B_0x0, SDMMCSEL=B_0x0, OTGFSSEL=B_0x0, ADFSEL=B_0x0, FMCSEL=B_0x0, ETHPHY_CLK_SEL=B_0x0, PSSISEL=B_0x0, ETH1_REF_CLK_SEL=B_0x0, USBPHYCSEL=B_0x0, ADCSEL=B_0x0, OCTOSPI2SEL=B_0x0, OCTOSPI1SEL=B_0x0
RCC AHB peripheral kernel clock selection register
| FMCSEL | FMC kernel clock source selection Set and reset by software. 0 (B_0x0): hclk5 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll1_q_ck selected as kernel peripheral clock 2 (B_0x2): pll2_r_ck selected as kernel peripheral clock 3 (B_0x3): hsi_ker_ck selected as kernel peripheral clock |
| SDMMCSEL | SDMMC1 and SDMMC2 kernel clock source selection Set and reset by software. 0 (B_0x0): pll2_s_ck selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll2_t_ck selected as kernel peripheral clock |
| OCTOSPI1SEL | XSPI1 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock 0 (B_0x0): hclk5 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll2_s_ck selected as kernel peripheral clock |
| OCTOSPI2SEL | XSPI2 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock 0 (B_0x0): hclk5 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll2_s_ck selected as kernel peripheral clock |
| USBREFCKSEL | USBPHYC kernel clock frequency selection Set and reset by software. This field is used to indicate to the USBPHYC, the frequency of the reference kernel clock provided to the USBPHYC. others: reserved 3 (B_0x3): The kernel clock frequency provided to the USBPHYC is 16 MHz 8 (B_0x8): The kernel clock frequency provided to the USBPHYC is 19.2 MHz 9 (B_0x9): The kernel clock frequency provided to the USBPHYC is 20MHz 10 (B_0xA): The kernel clock frequency provided to the USBPHYC is 24 MHz (default after reset) 11 (B_0xB): The kernel clock frequency provided to the USBPHYC is 32 MHz 14 (B_0xE): The kernel clock frequency provided to the USBPHYC is 26 MHz |
| USBPHYCSEL | USBPHYC kernel clock source selection Set and reset by software. 0 (B_0x0): hse_ker_ck (default after reset) 1 (B_0x1): hse_ker_ck / 2 2 (B_0x2): pll3_q_ck 3 (B_0x3): reserved, the kernel clock is disabled |
| OTGFSSEL | OTGFS kernel clock source selection Set and reset by software. 0 (B_0x0): hsi48_ker_ck (default after reset) 1 (B_0x1): pll3_q_ck 2 (B_0x2): hse_ker_ck 3 (B_0x3): clk48mohci |
| ETH1_REF_CLK_SEL | Ethernet reference clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): PAD ETH_RMII_REF_CLK selected as kernel peripheral clock (default after reset) 1 (B_0x1): hse_ker_ck selected as kernel peripheral clock 2 (B_0x2): eth_clk_fb selected as kernel peripheral clock |
| ETHPHY_CLK_SEL | Clock source selection for external Ethernet PHY Set and reset by software. 0 (B_0x0): hse_ker_ck selected as clock source (default after reset) 1 (B_0x1): pll3_s_ck selected clock source |
| ADFSEL | ADF kernel clock source selection Set and reset by software. Note: I2S_CKIN is an external clock taken from a pin. 0 (B_0x0): hclk1 selected as ADF kernel clock (default after reset) 1 (B_0x1): pll2_p_ck selected as ADF kernel clock |
| ADCSEL | SAR ADC kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): pll2_p_ck selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll3_r_ck selected as kernel peripheral clock 2 (B_0x2): per_ck selected as kernel peripheral clock |
| PSSISEL | PSSI kernel clock source selection Set and reset by software. 0 (B_0x0): pll3_r_ck selected as kernel peripheral clock (default after reset) 1 (B_0x1): per_ck selected as kernel peripheral clock |
| CKPERSEL | per_ck clock source selection 0 (B_0x0): hsi_ker_ck selected as per_ck clock (default after reset) 1 (B_0x1): csi_ker_ck selected as per_ck clock 2 (B_0x2): hse_ker_ck selected as per_ck clock 3 (B_0x3): reserved, the ck_per clock is disabled |