USART2EN=B_0x0, WWDGEN=B_0x0, HDMICECEN=B_0x0, TIM12EN=B_0x0, LPTIM1EN=B_0x0, TIM13EN=B_0x0, UART7EN=B_0x0, TIM5EN=B_0x0, I2C3EN=B_0x0, USART3EN=B_0x0, UART4EN=B_0x0, I2C2EN=B_0x0, UART8EN=B_0x0, SPI3EN=B_0x0, TIM4EN=B_0x0, TIM6EN=B_0x0, I2C1_I3C1EN=B_0x0, UART5EN=B_0x0, TIM2EN=B_0x0, TIM7EN=B_0x0, TIM3EN=B_0x0, TIM14EN=B_0x0, SPDIFRXEN=B_0x0, SPI2EN=B_0x0
RCC APB1 clock enable register 1
| TIM2EN | TIM2 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM2 peripheral clock disabled (default after reset) 1 (B_0x1): TIM2 peripheral clock enabled |
| TIM3EN | TIM3 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM3 peripheral clock disabled (default after reset) 1 (B_0x1): TIM3 peripheral clock enabled |
| TIM4EN | TIM4 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM4 peripheral clock disable (default after reset) 1 (B_0x1): TIM4 peripheral clock enabled |
| TIM5EN | TIM5 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM5 peripheral clock disabled (default after reset) 1 (B_0x1): TIM5 peripheral clock enabled |
| TIM6EN | TIM6 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM6 peripheral clock disabled (default after reset) 1 (B_0x1): TIM6 peripheral clock enabled |
| TIM7EN | TIM7 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM7 peripheral clock disabled (default after reset) 1 (B_0x1): TIM7 peripheral clock enabled |
| TIM12EN | TIM12 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM12 peripheral clock disabled (default after reset) 1 (B_0x1): TIM12 peripheral clock enabled |
| TIM13EN | TIM13 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM13 peripheral clock disabled (default after reset) 1 (B_0x1): TIM13 peripheral clock enabled |
| TIM14EN | TIM14 peripheral clock enable Set and reset by software. 0 (B_0x0): TIM14 peripheral clock disabled (default after reset) 1 (B_0x1): TIM14 peripheral clock enabled |
| LPTIM1EN | LPTIM1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to clk_lpt input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): LPTIM1 peripheral clocks disabled (default after reset) 1 (B_0x1): LPTIM1 peripheral clocks enabled |
| WWDGEN | WWDG clock enable Set by software, and reset by hardware when a system reset occurs. 0 (B_0x0): WWDG peripheral clock disable (default after reset) 1 (B_0x1): WWDG peripheral clock enabled |
| SPI2EN | SPI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): SPI2 peripheral clocks disabled (default after reset) 1 (B_0x1): SPI2 peripheral clocks enabled |
| SPI3EN | SPI3 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): SPI3 peripheral clocks disabled (default after reset) 1 (B_0x1): SPI3 peripheral clocks enabled |
| SPDIFRXEN | SPDIFRX peripheral clocks enable Set and reset by software. The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to SPDIFRX_CLK input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): SPDIFRX peripheral clocks disabled (default after reset) 1 (B_0x1): SPDIFRX peripheral clocks enabled |
| USART2EN | USART2peripheral clocks enable Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): USART2 peripheral clocks disabled (default after reset) 1 (B_0x1): USART2 peripheral clocks enabled |
| USART3EN | USART3 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): USART3 peripheral clocks disabled (default after reset) 1 (B_0x1): USART3 peripheral clocks enabled |
| UART4EN | UART4 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. 0 (B_0x0): UART4 peripheral clocks disabled (default after reset) 1 (B_0x1): UART4 peripheral clocks enabled |
| UART5EN | UART5 peripheral clocks enable Set and reset by software. 0 (B_0x0): UART5 peripheral clocks disabled (default after reset) 1 (B_0x1): UART5 peripheral clocks enabled |
| I2C1_I3C1EN | I2C1/I3C1 peripheral clocks enable Set and reset by software. 0 (B_0x0): I2C1/I3C1 peripheral clocks disabled (default after reset) 1 (B_0x1): I2C1/I3C1 peripheral clocks enabled |
| I2C2EN | I2C2 peripheral clocks enable Set and reset by software. 0 (B_0x0): I2C2 peripheral clocks disabled (default after reset) 1 (B_0x1): I2C2 peripheral clocks enabled |
| I2C3EN | I2C3 peripheral clocks enable Set and reset by software. 0 (B_0x0): I2C3 peripheral clocks disabled (default after reset) 1 (B_0x1): I2C3 peripheral clocks enabled |
| HDMICECEN | HDMI-CEC peripheral clock enable Set and reset by software. 0 (B_0x0): HDMI-CEC peripheral clock disabled (default after reset) 1 (B_0x1): HDMI-CEC peripheral clock enabled |
| UART7EN | UART7 peripheral clocks enable Set and reset by software. 0 (B_0x0): UART7 peripheral clocks disabled (default after reset) 1 (B_0x1): UART7 peripheral clocks enabled |
| UART8EN | UART8 peripheral clocks enable Set and reset by software. 0 (B_0x0): UART8 peripheral clocks disabled (default after reset) 1 (B_0x1): UART8 peripheral clocks enabled |