stm32 /stm32h7rs /STM32H7R /RCC /RCC_APB1ENR2

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Interpret as RCC_APB1ENR2

UCPDEN=B_0x0, CRSEN=B_0x0, FDCANEN=B_0x0, MDIOSEN=B_0x0

Description

RCC APB1 clock enable register 2

Fields

CRSEN	clock recovery system peripheral clock enable Set and reset by software. 0 (B_0x0): CRS peripheral clock disabled (default after reset) 1 (B_0x1): CRS peripheral clock enabled
MDIOSEN	MDIOS peripheral clock enable Set and reset by software. 0 (B_0x0): MDIOS peripheral clock disabled (default after reset) 1 (B_0x1): MDIOS peripheral clock enabled
FDCANEN	FDCAN peripheral clock enable Set and reset by software. 0 (B_0x0): FDCAN peripheral clock disabled (default after reset) 1 (B_0x1): FDCAN peripheral clock enabled
UCPDEN	UCPD peripheral clock enable Set and reset by software. 0 (B_0x0): UCPD peripheral clock disabled (default after reset) 1 (B_0x1): UCPD peripheral clock enabled

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