LPTIM1SEL=B_0x0, SPDIFRXSEL=B_0x0, SPI23SEL=B_0x0, CECSEL=B_0x0, I2C23SEL=B_0x0, FDCANSEL=B_0x0, UART234578SEL=B_0x0, I2C1_I3C1SEL=B_0x0
RCC APB1 peripherals kernel clock selection register
| UART234578SEL | USART2,3, UART4,5,7,8 (APB1) kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): pclk1 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock |
| SPI23SEL | SPI/I2S2 and SPI/I2S3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. 0 (B_0x0): pll1_q_ck selected as kernel clock (default after reset) 1 (B_0x1): pll2_p_ck selected as kernel clock 2 (B_0x2): pll3_p_ck selected as kernel clock 3 (B_0x3): I2S_CKIN selected as kernel clock 4 (B_0x4): per_ck selected as kernel clock |
| I2C23SEL | I2C2, I2C3 kernel clock source selection Set and reset by software. 0 (B_0x0): pclk1 selected as kernel clock (default after reset) 1 (B_0x1): pll3_r_ck selected as kernel clock 2 (B_0x2): hsi_ker_ck selected as kernel clock 3 (B_0x3): csi_ker_ck selected as kernel clock |
| I2C1_I3C1SEL | I2C1 or I3C1 kernel clock source selection Set and reset by software. 0 (B_0x0): pclk1 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll3_r_ck selected as kernel peripheral clock 2 (B_0x2): hsi_ker_ck selected as kernel peripheral clock 3 (B_0x3): csi_ker_ck selected as kernel peripheral clock |
| LPTIM1SEL | LPTIM1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): pclk1 selected as kernel peripheral clock (default after reset) 1 (B_0x1): pll2_p_ck selected as kernel peripheral clock 2 (B_0x2): pll3_r_ck selected as kernel peripheral clock 3 (B_0x3): lse_ck selected as kernel peripheral clock 4 (B_0x4): lsi_ck selected as kernel peripheral clock 5 (B_0x5): per_ck selected as kernel peripheral clock |
| FDCANSEL | FDCAN kernel clock source selection 0 (B_0x0): hse_ker_ck selected as FDCAN kernel clock (default after reset) 1 (B_0x1): pll1_q_ck selected as FDCAN kernel clock 2 (B_0x2): pll2_p_ck selected as FDCAN kernel clock 3 (B_0x3): reserved, the kernel clock is disabled |
| SPDIFRXSEL | SPDIFRX kernel clock source selection 0 (B_0x0): pll1_q_ck selected as SPDIFRX kernel clock (default after reset) 1 (B_0x1): pll2_r_ck selected as SPDIFRX kernel clock 2 (B_0x2): pll3_r_ck selected as SPDIFRX kernel clock 3 (B_0x3): hsi_ker_ck selected as SPDIFRX kernel clock |
| CECSEL | HDMI-CEC kernel clock source selection Set and reset by software. 0 (B_0x0): lse_ck selected as kernel clock (default after reset) 1 (B_0x1): lsi_ck selected as kernel clock 2 (B_0x2): csi_ker_ck divided by 122 selected as kernel clock 3 (B_0x3): reserved, the kernel clock is disabled |