RTCSEL=B_0x0, RTCEN=B_0x0, LSEBYP=B_0x0, LSECSSRA=B_0x0, VSWRST=B_0x0, LSEEXT=B_0x0, LSECSSD=B_0x0, LSERDY=B_0x0, LSECSSON=B_0x0, LSEON=B_0x0, LSEDRV=B_0x0
RCC Backup domain control register
| LSEON | LSE oscillator enabled Set and reset by software. 0 (B_0x0): LSE oscillator OFF (default after Backup domain reset) 1 (B_0x1): LSE oscillator ON |
| LSERDY | LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0. 0 (B_0x0): LSE oscillator not ready (default after Backup domain reset) 1 (B_0x1): LSE oscillator ready |
| LSEBYP | LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1) 0 (B_0x0): LSE oscillator not bypassed (default after Backup domain reset) 1 (B_0x1): LSE oscillator bypassed |
| LSEDRV | LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. 0 (B_0x0): lowest drive (default after Backup domain reset) 1 (B_0x1): medium-low drive 2 (B_0x2): medium-high drive 3 (B_0x3): highest drive |
| LSECSSON | LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit can only be disabled, After a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. After a back-up domain reset 0 (B_0x0): CSS on 32 kHz oscillator OFF (default after Backup domain reset) 1 (B_0x1): CSS on 32 kHz oscillator ON |
| LSECSSD | LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator. 0 (B_0x0): no failure detected on 32 kHz oscillator (default after Backup domain reset) 1 (B_0x1): failure detected on 32 kHz oscillator |
| LSEEXT | low-speed external clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled. 0 (B_0x0): LSE in analog mode (default after Backup domain reset) 1 (B_0x1): LSE in digital mode (do not use if RTC is active). |
| RTCSEL | RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST). 0 (B_0x0): no clock (default after Backup domain reset) 1 (B_0x1): LSE selected as RTC clock 2 (B_0x2): LSI selected as RTC clock 3 (B_0x3): HSE divided by RTCPRE value selected as RTC clock |
| LSECSSRA | Re-Arm the LSECSS function Set by software. After a LSE failure detection, the software application can re-enable the LSECSS by writing this bit to 1. Reading this bit returns the written value. Prior to set this bit to 1, LSECSSON must be set to 0. Please refer to Section : CSS on LSE for details. 0 (B_0x0): Writing 0 has no effect (default after Backup domain reset) 1 (B_0x1): Writing 1 generates a re-arm pulse for the LSECSS function |
| RTCEN | RTC clock enable Set and reset by software. 0 (B_0x0): rtc_ck disabled (default after Backup domain reset) 1 (B_0x1): rtc_ck enabled |
| VSWRST | VSwitch domain software reset Set and reset by software. To generate a VSW reset, it is recommended to write this bit to 1, then back to 0. 0 (B_0x0): reset not activated (default after Backup domain reset) 1 (B_0x1): generates a reset pulse, resetting the entire VSW domain. |