RCC AHB clock configuration register
| BMPRE | Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk[5:1] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk[5:1] = rcc_aclk = sys_bus_ck. 8 (B_0x8): sys_bus_ck = sys_cpu_ck / 2 9 (B_0x9): sys_bus_ck= sys_cpu_ck / 4 10 (B_0xA): sys_bus_ck = sys_cpu_ck / 8 11 (B_0xB): sys_bus_ck = sys_cpu_ck / 16 12 (B_0xC): sys_bus_ck = sys_cpu_ck / 64 13 (B_0xD): sys_bus_ck = sys_cpu_ck / 128 14 (B_0xE): sys_bus_ck = sys_cpu_ck / 256 15 (B_0xF): sys_bus_ck = sys_cpu_ck / 512 |