RCC CPU domain clock configuration register
| CPRE | CPU domain core prescaler Set and reset by software to control the CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks. After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset) 8 (B_0x8): sys_ck divided by 2 9 (B_0x9): sys_ck divided by 4 10 (B_0xA): sys_ck divided by 8 11 (B_0xB): sys_ck divided by 16 12 (B_0xC): sys_ck divided by 64 13 (B_0xD): sys_ck divided by 128 14 (B_0xE): sys_ck divided by 256 15 (B_0xF): sys_ck divided by 512 |