HSERDYF=B_0x0, CSIRDYF=B_0x0, HSECSSF=B_0x0, PLL2RDYF=B_0x0, LSIRDYF=B_0x0, HSIRDYF=B_0x0, PLL3RDYF=B_0x0, PLL1RDYF=B_0x0, LSERDYF=B_0x0, LSECSSF=B_0x0, HSI48RDYF=B_0x0
RCC clock source interrupt flag register
| LSIRDYF | LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. 0 (B_0x0): no clock ready interrupt caused by the LSI (default after reset) 1 (B_0x1): clock ready interrupt caused by the LSI |
| LSERDYF | LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set. 0 (B_0x0): no clock ready interrupt caused by the LSE (default after reset) 1 (B_0x1): clock ready interrupt caused by the LSE |
| HSIRDYF | HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set. 0 (B_0x0): no clock ready interrupt caused by the HSI (default after reset) 1 (B_0x1): clock ready interrupt caused by the HSI |
| HSERDYF | HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. 0 (B_0x0): no clock ready interrupt caused by the HSE (default after reset) 1 (B_0x1): clock ready interrupt caused by the HSE |
| CSIRDYF | CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set. 0 (B_0x0): no clock ready interrupt caused by the CSI (default after reset) 1 (B_0x1): clock ready interrupt caused by the CSI |
| HSI48RDYF | HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. 0 (B_0x0): no clock ready interrupt caused by the HSI48 oscillator (default after reset) 1 (B_0x1): clock ready interrupt caused by the HSI48 oscillator |
| PLL1RDYF | PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. 0 (B_0x0): no clock ready interrupt caused by PLL1 lock (default after reset) 1 (B_0x1): clock ready interrupt caused by PLL1 lock |
| PLL2RDYF | PLL2 ready interrupt flag Reset by software by writing PLL2RDYC bit. Set by hardware when the PLL2 locks and PLL2RDYIE is set. 0 (B_0x0): no clock ready interrupt caused by PLL2 lock (default after reset) 1 (B_0x1): clock ready interrupt caused by PLL2 lock |
| PLL3RDYF | PLL3 ready interrupt flag Reset by software by writing PLL3RDYC bit. Set by hardware when the PLL3 locks and PLL3RDYIE is set. 0 (B_0x0): no clock ready interrupt caused by PLL3 lock (default after reset) 1 (B_0x1): clock ready interrupt caused by PLL3 lock |
| LSECSSF | LSE clock security system interrupt flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set. 0 (B_0x0): no failure detected on the external 32 kHz oscillator (default after reset) 1 (B_0x1): failure detected on the external 32 kHz oscillator |
| HSECSSF | HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. 0 (B_0x0): no clock security interrupt caused by HSE clock failure (default after reset) 1 (B_0x1): clock security interrupt caused by HSE clock failure |