AXIRAM2CKG=B_0x0, AXICKG=B_0x0, EXTICKG=B_0x0, HPDMA1CKG=B_0x0, DMA2DCKG=B_0x0, GPUS1CKG=B_0x0, JTAGCKG=B_0x0, LTDCCKG=B_0x0, FMCCKG=B_0x0, AXIRAM1CKG=B_0x0, AHBSCKG=B_0x0, GPUS0CKG=B_0x0, SDMMC1CKG=B_0x0, CPUCKG=B_0x0, AHBMCKG=B_0x0, XSPI1CKG=B_0x0, AXIRAM4CKG=B_0x0, XSPI2CKG=B_0x0, GFXMMUSCKG=B_0x0, AXIRAM3CKG=B_0x0, DCMIPPCKG=B_0x0, GPUCLCKG=B_0x0, FLITFCKG=B_0x0, GFXMMUMCKG=B_0x0
RCC AXI clocks gating disable register
| AXICKG | AXI interconnect matrix clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The AXI interconnect matrix clock is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled |
| AHBMCKG | AXI master AHB clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI master port connected to the AHB interconnect is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| SDMMC1CKG | AXI master SDMMC1 clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI master port connected to SDMMC1 is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| HPDMA1CKG | AXI master HPDMA1 clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI master port connected to the HPDMA1 is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled |
| CPUCKG | AXI master CPU clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI master port connected to the CPU is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| GPUS0CKG | AXI master 0 GPU clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI master port connected to the GPU port 0 is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| GPUS1CKG | AXI master 1 GPU clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI master port connected to the GPU port 1 is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| GPUCLCKG | AXI master cache GPU clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI master port connected to the GPU I-Cache is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| DCMIPPCKG | AXI master DCMIPP clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI master port connected to the DCMIPP is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| DMA2DCKG | AXI master DMA2D clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI master port connected to the DMA2D is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled |
| GFXMMUSCKG | AXI matrix slave GFXMMU clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI slave port connected to the GFXMMU is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled |
| LTDCCKG | AXI master LTDC clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI master port connected to the LTDC is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| GFXMMUMCKG | AXI master GFXMMU clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI master port connected to the GFXMMU is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled |
| AHBSCKG | AXI slave AHB clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The AXI matrix slave AHB clock is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled |
| FMCCKG | AXI slave FMC and MCE3 clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI slave port connected to the FMC and MCE3 is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| XSPI1CKG | AXI slave XSPI1 and MCE1 clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI slave port connected to the XSPI1 and MCE1 is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| XSPI2CKG | AXI slave XSPI2 and MCE2 clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI slave port connected to the XSPI2 and MCE2 is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| AXIRAM4CKG | AXI matrix slave SRAM4 clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI slave port connected to the SRAM4 is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| AXIRAM3CKG | AXI matrix slave SRAM3 clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI slave port connected to the SRAM3 is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| AXIRAM2CKG | AXI slave SRAM2 clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI slave port connected to the SRAM2 is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| AXIRAM1CKG | AXI slave SRAM1 / error code correction (ECC) clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI slave port connected to the SRAM1 is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| FLITFCKG | AXI slave Flash interface (FLIFT) clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock of the AXI slave port connected to the FLITF is enabled on bus transaction request. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| EXTICKG | EXTI clock gating disable This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock is enabled after an event detection and stopped again when the event flag is cleared. (default after reset) 1 (B_0x1): The clock gating is disabled. The clock is always enabled. |
| JTAGCKG | JTAG automatic clock gating disabling This bit is set and reset by software. 0 (B_0x0): The clock gating is enabled. The clock is disabled except if a JTAG connection has been detected 1: The clock gating is disabled. The clock is always enabled. (default after reset) |