stm32 /stm32h7rs /STM32H7R /RCC /RCC_CR

HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 0 or STOPKERWUCK = 0. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW switch) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1.

0 (B_0x0): HSI is OFF

1 (B_0x1): HSI is ON (default after reset)

HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION.

0 (B_0x0): no effect on HSI (default after reset)

1 (B_0x1): HSI is forced to ON even in Stop mode

HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable.

0 (B_0x0): HSI clock is not ready (default after reset)

1 (B_0x1): HSI clock is ready

HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored.

0 (B_0x0): division by 1, hsi(_ker)_ck = 64 MHz (default after reset)

1 (B_0x1): division by 2, hsi(_ker)_ck = 32 MHz

2 (B_0x2): division by 4, hsi(_ker)_ck = 16 MHz

3 (B_0x3): division by 8, hsi(_ker)_ck = 8 MHz

HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. clock setting is completed)

0 (B_0x0): new division ratio not yet propagated to hsi(_ker)_ck (default after reset)

1 (B_0x1): hsi(_ker)_ck clock frequency reflects the new HSIDIV value (default register value when the

CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1.

0 (B_0x0): CSI is OFF (default after reset)

1 (B_0x1): CSI is ON

CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request).

0 (B_0x0): CSI clock is not ready (default after reset)

1 (B_0x1): CSI clock is ready

CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION.

0 (B_0x0): no effect on CSI (default after reset)

1 (B_0x1): CSI is forced to ON even in Stop mode

HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode.

0 (B_0x0): HSI48 is OFF (default after reset)

1 (B_0x1): HSI48 is ON

HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable.

0 (B_0x0): HSI48 clock is not ready (default after reset)

1 (B_0x1): HSI48 clock is ready

HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1.

0 (B_0x0): HSE is OFF (default after reset)

1 (B_0x1): HSE is ON

HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable.

0 (B_0x0): HSE clock is not ready (default after reset)

1 (B_0x1): HSE clock is ready

HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.

0 (B_0x0): HSE oscillator not bypassed (default after reset)

1 (B_0x1): HSE oscillator bypassed with an external clock

external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled.

0 (B_0x0): HSE in analog mode (default after reset)

1 (B_0x1): HSE in digital mode

HSE clock security system enable Set by software to enable clock security system on HSE. This bit is set only (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected.

0 (B_0x0): CSS on HSE OFF (clock detector OFF) (default after reset)

1 (B_0x1): CSS on HSE ON (clock detector ON if the HSE oscillator is stable, OFF if not).

PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCKP = 1, or if XSPICKP = 1.

0 (B_0x0): PLL1 OFF (default after reset)

1 (B_0x1): PLL1 ON

PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked.

0 (B_0x0): PLL1 unlocked (default after reset)

1 (B_0x1): PLL1 locked

PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if FMCCKP = 1, or XSPICKP = 1.

0 (B_0x0): PLL2 OFF (default after reset)

1 (B_0x1): PLL2 ON

PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked.

0 (B_0x0): PLL2 unlocked (default after reset)

1 (B_0x1): PLL2 locked

PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop or Standby mode.

0 (B_0x0): PLL3 OFF (default after reset)

1 (B_0x1): PLL3 ON

PLL3 clock ready flag Set by hardware to indicate that the PLL3 is locked.

0 (B_0x0): PLL3 unlocked (default after reset)

1 (B_0x1): PLL3 locked