DIVP=B_0x0, DIVR1=B_0x0, DIVQ=B_0x0
RCC PLL1 dividers configuration register 1
| DIVN1 | multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0). …: not used … … Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x DIVN1, when fractional value 0 has been loaded into FRACN, with: DIVN1 between 8 and 420 The input frequency Fref1_ck must be between 1 and 16 MHz. 6 (B_0x006): wrong configuration 7 (B_0x007): DIVN1 = 8 128 (B_0x080): DIVN1 = 129 (default after reset) 419 (B_0x1A3): DIVN1 = 420 |
| DIVP | PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1DIVPEN = 0. … 0 (B_0x0): not allowed 1 (B_0x1): pll1_p_ck = vco1_ck / 2 (default after reset) 2 (B_0x2): not allowed 3 (B_0x3): pll1_p_ck = vco1_ck / 4 127 (B_0x7F): pll1_p_ck = vco1_ck / 128 |
| DIVQ | PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1DIVQEN = 0. … 0 (B_0x0): pll1_q_ck = vco1_ck 1 (B_0x1): pll1_q_ck = vco1_ck / 2 (default after reset) 2 (B_0x2): pll1_q_ck = vco1_ck / 3 3 (B_0x3): pll1_q_ck = vco1_ck / 4 127 (B_0x7F): pll1_q_ck = vco1_ck / 128 |
| DIVR1 | PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1DIVREN = 0. … 0 (B_0x0): pll1_r_ck = vco1_ck 1 (B_0x1): pll1_r_ck = vco1_ck / 2 (default after reset) 2 (B_0x2): pll1_r_ck = vco1_ck / 3 3 (B_0x3): pll1_r_ck = vco1_ck / 4 127 (B_0x7F): pll1_r_ck = vco1_ck / 128 |