PLL1DIVTEN=B_0x0, PLL3DIVREN=B_0x0, PLL2DIVPEN=B_0x0, PLL2DIVTEN=B_0x0, PLL1VCOSEL=B_0x0, PLL3DIVTEN=B_0x0, PLL3DIVSEN=B_0x0, PLL2DIVQEN=B_0x0, PLL3SSCGEN=B_0x0, PLL2VCOSEL=B_0x0, PLL3DIVPEN=B_0x0, PLL2DIVSEN=B_0x0, PLL2DIVREN=B_0x0, PLL1DIVSEN=B_0x0, PLL3DIVQEN=B_0x0, PLL1DIVREN=B_0x0, PLL1DIVQEN=B_0x0, PLL1DIVPEN=B_0x0, PLL1RGE=B_0x0, PLL1SSCGEN=B_0x0, PLL3VCOSEL=B_0x0, PLL2SSCGEN=B_0x0, PLL3RGE=B_0x0, PLL2RGE=B_0x0
RCC PLLs configuration register
| PLL1FRACLE | PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. |
| PLL1VCOSEL | PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref1_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref1_ck must be between 1 and 2 MHz) 0 (B_0x0): VCOH selected (default after reset) 1 (B_0x1): VCOL selected |
| PLL1SSCGEN | PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks. 0 (B_0x0): SSCG disabled (default after reset) 1 (B_0x1): SSCG enabled |
| PLL1RGE | PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 0 (B_0x0): PLL1 input (ref1_ck) clock range frequency between 1 and 2 MHz (default after reset) 1 (B_0x1): PLL1 input (ref1_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz |
| PLL1DIVPEN | PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. 0 (B_0x0): pll1_p_ck output disabled (default after reset) 1 (B_0x1): pll1_p_ck output enabled |
| PLL1DIVQEN | PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. 0 (B_0x0): pll1_q_ck output disabled (default after reset) 1 (B_0x1): pll1_q_ck output enabled |
| PLL1DIVREN | PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. 0 (B_0x0): pll1_r_ck output disabled (default after reset) 1 (B_0x1): pll1_r_ck output enabled |
| PLL1DIVSEN | PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used. 0 (B_0x0): pll1_s_ck output disabled (default after reset) 1 (B_0x1): pll1_s_ck output enabled |
| PLL1DIVTEN | PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used. 0 (B_0x0): pll1_t_ck output disabled (default after reset) 1 (B_0x1): pll1_t_ck output enabled |
| PLL2FRACLE | PLL2 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL2FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. |
| PLL2VCOSEL | PLL2 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL2. This bit must be written before enabling the PLL2. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref2_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref2_ck must be between 1 and 2 MHz) 0 (B_0x0): VCOH selected (default after reset) 1 (B_0x1): VCOL selected |
| PLL2SSCGEN | PLL2 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL2, in order to reduce the amount of EMI peaks. 0 (B_0x0): SSCG disabled (default after reset) 1 (B_0x1): SSCG enabled |
| PLL2RGE | PLL2 input frequency range Set and reset by software to select the proper reference frequency range used for PLL2. These bits must be written before enabling the PLL2. 0 (B_0x0): PLL3 input (ref2_ck) clock range frequency between 1 and 2 MHz (default after reset) 1 (B_0x1): PLL3 input (ref2_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL3 input (ref2_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL3 input (ref2_ck) clock range frequency between 8 and 16 MHz |
| PLL2DIVPEN | PLL2 DIVP divider output enable Set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2DIVPEN and DIVP bits must be set to 0 when the pll2_p_ck is not used. 0 (B_0x0): pll2_p_ck output disabled (default after reset) 1 (B_0x1): pll2_p_ck output enabled |
| PLL2DIVQEN | PLL2 DIVQ divider output enable Set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL3DIVQEN and DIVQ bits must be set to 0 when the pll2_q_ck is not used. 0 (B_0x0): pll2_q_ck output disabled (default after reset) 1 (B_0x1): pll2_q_ck output enabled |
| PLL2DIVREN | PLL2 DIVR divider output enable Set and reset by software to enable the pll2_r_ck output of the PLL2. The hardware prevents writing this bit if FMCCKP = 1. To save power, PLL3DIVREN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. 0 (B_0x0): pll2_r_ck output disabled (default after reset) 1 (B_0x1): pll2_r_ck output enabled |
| PLL2DIVSEN | PLL2 DIVS divider output enable Set and reset by software to enable the pll2_s_ck output of the PLL2. To save power, PLL2DIVSEN must be set to 0 when the pll2_s_ck is not used. The hardware prevents writing this bit if XSPICKP = 1. 0 (B_0x0): pll2_s_ck output disabled (default after reset) 1 (B_0x1): pll2_s_ck output enabled |
| PLL2DIVTEN | PLL2 DIVT divider output enable Set and reset by software to enable the pll2_t_ck output of the PLL2. To save power, PLL2DIVTEN must be set to 0 when the pll2_t_ck is not used. The hardware prevents writing this bit if XSPICKP = 1. 0 (B_0x0): pll2_t_ck output disabled (default after reset) 1 (B_0x1): pll2_t_ck output enabled |
| PLL3FRACLE | PLL3 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL3FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. |
| PLL3VCOSEL | PLL3 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL3. This bit must be written before enabling the PLL3. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref2_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref2_ck must be between 1 and 2 MHz) 0 (B_0x0): VCOH selected (default after reset) 1 (B_0x1): VCOL selected |
| PLL3SSCGEN | PLL3 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL3, in order to reduce the amount of EMI peaks. 0 (B_0x0): SSCG disabled (default after reset) 1 (B_0x1): SSCG enabled |
| PLL3RGE | PLL3 input frequency range Set and reset by software to select the proper reference frequency range used for PLL3. These bits must be written before enabling the PLL3. 0 (B_0x0): PLL3 input (ref3_ck) clock range frequency between 1 and 2 MHz (default after reset) 1 (B_0x1): PLL3 input (ref3_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz |
| PLL3DIVPEN | PLL3 DIVP divider output enable Set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3DIVREN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. 0 (B_0x0): pll3_p_ck output disabled (default after reset) 1 (B_0x1): pll3_p_ck output enabled |
| PLL3DIVQEN | PLL3 DIVQ divider output enable Set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3DIVREN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. 0 (B_0x0): pll3_q_ck output disabled (default after reset) 1 (B_0x1): pll3_q_ck output enabled |
| PLL3DIVREN | PLL3 DIVR divider output enable Set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3DIVREN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. 0 (B_0x0): pll3_r_ck output disabled (default after reset) 1 (B_0x1): pll3_r_ck output enabled |
| PLL3DIVSEN | PLL3 DIVS divider output enable Set and reset by software to enable the pll3_s_ck output of the PLL3. To save power, PLL3DIVSEN must be set to 0 when the pll3_s_ck is not used. 0 (B_0x0): pll3_s_ck output disabled (default after reset) 1 (B_0x1): pll3_s_ck output enabled |
| PLL3DIVTEN | PLL3 DIVT divider output enable Set and reset by software to enable the pll3_t_ck output of the PLL3. To save power, PLL1DIVTEN must be set to 0 when the pll3_t_ck is not used. 0 (B_0x0): pll3_t_ck output disabled (default after reset) 1 (B_0x1): pll3_t_ck output enabled |