SFTRSTF=B_0x0, PORRSTF=B_0x0, PINRSTF=B_0x0, OBLRSTF=B_0x0, RMVF=B_0x0, IWDGRSTF=B_0x0, WWDGRSTF=B_0x0, BORRSTF=B_0x0, LPWRRSTF=B_0x0
RCC Reset status register
| RMVF | remove reset flag Set and reset by software to reset the value of the reset flags. 0 (B_0x0): reset of the reset flags not activated (default after power-on reset) 1 (B_0x1): resets the value of the reset flags |
| OBLRSTF | Option byte loading reset flag (1) Reset by software by the RMVF bit. Set by hardware when a reset from the option byte loading occurs. 0 (B_0x0): No reset from option byte loading occurred 1 (B_0x1): Reset from option byte loading occurred |
| BORRSTF | BOR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). 0 (B_0x0): no BOR reset occurred 1 (B_0x1): BOR reset occurred (default after power-on reset) |
| PINRSTF | pin reset flag (NRST) (1) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. 0 (B_0x0): no reset from pin occurred 1 (B_0x1): reset from pin occurred (default after power-on reset) |
| PORRSTF | POR/PDR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs. 0 (B_0x0): no POR/PDR reset occurred 1 (B_0x1): POR/PDR reset occurred (default after power-on reset) |
| SFTRSTF | system reset from CPU reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7. 0 (B_0x0): no CPU software reset occurred (default after power-on reset) 1 (B_0x1): a system reset has been generated by the CPU |
| IWDGRSTF | independent watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. 0 (B_0x0): no independent watchdog reset occurred (default after power-on reset) 1 (B_0x1): independent watchdog reset occurred |
| WWDGRSTF | window watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. 0 (B_0x0): no window watchdog reset occurred from WWDG (default after power-on reset) 1 (B_0x1): window watchdog reset occurred from WWDG |
| LPWRRSTF | reset due to illegal Stop or Standby flag Reset by software by writing the RMVF bit. Set by hardware when the CPU goes erroneously in Stop or Standby mode, 0 (B_0x0): no illegal reset occurred (default after power-on reset) 1 (B_0x1): illegal Stop or Standby reset occurred |