PVD_BL=B_0x0, BKRAMECC_BL=B_0x0, ITCMECC_BL=B_0x0, ARAM1ECC_BL=B_0x0, ARAM3ECC_BL=B_0x0, FLASHECC_BL=B_0x0, CM7LCKUP_BL=B_0x0, DTCMECC_BL=B_0x0
SBS break lockup register
| PVD_BL | PVD break lock This bit is set by SW and cleared only by a system reset. it can be used to enable and lock the connection to TIM1/8/15/16/17Break input as well as the PVDE and PLS[2:0] bitfields in the PWR_CR1 register. Once set, this bit is cleared only by a system reset. 0 (B_0x0): PVD interrupt disconnected from TIM1/8/15/16/17 break inputs. PVDE and PLS[2:0] bitfields can be programmed by the application. 1 (B_0x1): PVD output connected to TIM1/8/15/16/17 break input. PVDE and PLS[2:0] bits are read only. |
| FLASHECC_BL | Flash ECC error break lock Set this bit to enable and lock the connection between embedded flash memory ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. 0 (B_0x0): FLASH ECC double error detection flag disconnected from TIM1/15/16/17 break inputs 1 (B_0x1): FLASH ECC double error detection flag connected to TIM1/15/16/17 break inputs |
| CM7LCKUP_BL | Cortex-M7 lockup break lock Set this bit to enable and lock the connection between the Cortex-M7 lockup (HardFault) output and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. 0 (B_0x0): Cortex-M7 lockup output disconnected from TIM1/15/16/17 break inputs 1 (B_0x1): Cortex-M7 lockup output connected to TIM1/15/16/17 break inputs |
| BKRAMECC_BL | Backup RAM ECC error break lock Set this bit to enable and lock the connection between backup RAM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. 0 (B_0x0): Backup RAM ECC double error detection flag disconnected from TIM1/15/16/17 break inputs. 1 (B_0x1): Backup RAM ECC double error detection flag connected to TIM1/15/16/17 break inputs. |
| DTCMECC_BL | DTCM ECC error break lock Set this bit to enable and lock the connection between DTCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. Note: The DTCM0 and DTCM1 are Ored to give DTCMECC 0 (B_0x0): DTCM ECC double error detection flag disconnected from TIM1/15/16/17 break inputs 1 (B_0x1): DTCM ECC double error detection flag connected to TIM1/15/16/17 break inputs |
| ITCMECC_BL | ITCM ECC error break lock Set this bit to enable and lock the connection between ITCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. 0 (B_0x0): ITCM ECC double error detection flag disconnected from TIM1/15/16/17 break inputs 1 (B_0x1): ITCM ECC double error detection flag connected to TIM1/15/16/17 break inputs |
| ARAM3ECC_BL | AXIRAM3 ECC error break lock Set this bit to enable and lock the connection between AXIRAM3 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set this bit is cleared only by a system reset. 0 (B_0x0): AXIRAM3 ECC double error detection flag disconnected from TIM1/15/16/17 break inputs 1 (B_0x1): AXIRAM3 ECC double error detection flag connected to TIM1/15/16/17 break inputs |
| ARAM1ECC_BL | AXIRAM1 ECC error break lock Set this bit to enable and lock the connection between AXIRAM1 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. 0 (B_0x0): AXIRAM1 ECC double error detection flag disconnected from TIM1/5/16/17 break inputs 1 (B_0x1): AXIRAM1 ECC double error detection flag connected to TIM1/15/16/17 break inputs |