ULS=B_0x0, ULA=B_0x0, ABR=B_0x0
SDMMC IDMA linked list address register
| IDMALA | Word aligned linked list item address offset Linked list item offset pointer to the base of the next linked list item structure. Linked list item base address is IDMABA + IDMALA. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). |
| ABR | Acknowledge linked list buffer ready This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is not taken into account when starting the first linked list buffer from the software programmed register information. ABR is only taken into account on subsequent loaded linked list items. 0 (B_0x0): Loaded linked list buffer is not ready (this causes a linked list IDMA transfer error to be generated). 1 (B_0x1): Loaded linked list buffer ready acknowledge. Linked list buffer data are transfered by IDMA. |
| ULS | Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1) This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 (B_0x0): SDMMC_IDMABSIZER is not to be updated from next linked list table. 1 (B_0x1): SDMMC_IDMABSIZER is to be updated from next linked list table. |
| ULA | Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode) This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 (B_0x0): SDMMC_IDMALAR is not to be updated, last linked list item. 1 (B_0x1): SDMMC_IDMALAR is to be updated from linked list table. |