BUSYD0END=B_0x0, BUSYD0=B_0x0
SDMMC status register
| CCRCFAIL | Command response received (CRC check failed) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| DCRCFAIL | Data block sent/received (CRC check failed) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| CTIMEOUT | Command response timeout Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. |
| DTIMEOUT | Data timeout Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| TXUNDERR | Transmit FIFO underrun error (masked by hardware when IDMA is enabled) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| RXOVERR | Received FIFO overrun error (masked by hardware when IDMA is enabled) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| CMDREND | Command response received (CRC check passed, or no CRC) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| CMDSENT | Command sent (no response required) Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| DATAEND | Data transfer ended correctly DATAEND is set if data counter DATACOUNT is zero and no errors occur, and no transmit data transfer hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| DHOLD | Data transfer Hold Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| DBCKEND | Data block sent/received DBCKEND is set when:
|
| DABORT | Data transfer aborted by CMD12 Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| DPSMACT | Data path state machine active, i.e. not in Idle state This is a hardware status flag only, does not generate an interrupt. |
| CPSMACT | Command path state machine active, i.e. not in Idle state This is a hardware status flag only, does not generate an interrupt. |
| TXFIFOHE | Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. |
| RXFIFOHF | Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. |
| TXFIFOF | Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. |
| RXFIFOF | Receive FIFO full This bit is cleared when one FIFO location becomes empty. |
| TXFIFOE | Transmit FIFO empty This bit is cleared when one FIFO location becomes full. |
| RXFIFOE | Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. |
| BUSYD0 | Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. 0 (B_0x0): card signals not busy on SDMMC_D0. 1 (B_0x1): card signals busy on SDMMC_D0. |
| BUSYD0END | end of SDMMC_D0 Busy following a CMD response detected This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 0 (B_0x0): card SDMMC_D0 signal does NOT signal change from busy to not busy. 1 (B_0x1): card SDMMC_D0 signal changed from busy to NOT busy. |
| SDIOIT | SDIO interrupt received The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| ACKFAIL | Boot acknowledgment received (boot acknowledgment check fail) The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| ACKTIMEOUT | Boot acknowledgment timeout The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| VSWEND | Voltage switch critical timing section completion The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| CKSTOP | SDMMC_CK stopped in Voltage switch procedure The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| IDMATE | IDMA transfer error The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |
| IDMABTC | IDMA buffer transfer complete The interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. |