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stm32 /stm32h7rs /STM32H7R /SPDIFRX /SPDIFRX_FMT0_DR_alternate1

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Interpret as SPDIFRX_FMT0_DR_alternate1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PE)PE 0 (V)V0 (U)U0 (C)C0 (B_0x0)PT0DR

PT=B_0x0

Description

SPDIFRX data input register

Fields

PE

parity error bit Contains a copy of PERR bit if PMSK = 0, otherwise it is forced to 0
V

validity bit Contains the received validity bit if VMSK = 0, otherwise it is forced to 0
U

user bit Contains the received user bit, if CUMSK = 0, otherwise it is forced to 0
C

channel Status bit Contains the received channel status bit, if CUMSK = 0, otherwise it is forced to 0
PT

preamble type These bits indicate the preamble received. Note that if PTMSK = 1, this field is forced to zero

0 (B_0x0): not used

1 (B_0x1): preamble B received

2 (B_0x2): preamble M received

3 (B_0x3): preamble W received
DR

data value Contains the 24 received data bits, aligned on D[23]

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32