SPDIFRX_IMR

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Interpret as SPDIFRX_IMR

OVRIE=B_0x0, SBLKIE=B_0x0, CSRNEIE=B_0x0, PERRIE=B_0x0, IFEIE=B_0x0, SYNCDIE=B_0x0, RXNEIE=B_0x0

Description

SPDIFRX interrupt mask register

Fields

RXNEIE	RXNE interrupt enable This bit is set and cleared by software. 0 (B_0x0): Interrupt is inhibited. 1 (B_0x1): A SPDIFRX interface interrupt is generated whenever RXNE=1 in the SPDIFRX_SR register.
CSRNEIE	Control buffer ready interrupt enable This bit is set and cleared by software. 0 (B_0x0): Interrupt is inhibited. 1 (B_0x1): A SPDIFRX interface interrupt is generated whenever CSRNE = 1 in the SPDIFRX_SR register.
PERRIE	Parity error interrupt enable This bit is set and cleared by software. 0 (B_0x0): Interrupt is inhibited. 1 (B_0x1): A SPDIFRX interface interrupt is generated whenever PERR=1 in the SPDIFRX_SR register.
OVRIE	Overrun error interrupt enable This bit is set and cleared by software. 0 (B_0x0): Interrupt is inhibited. 1 (B_0x1): A SPDIFRX interface interrupt is generated whenever OVR=1 in the SPDIFRX_SR register.
SBLKIE	Synchronization block detected interrupt enable This bit is set and cleared by software. 0 (B_0x0): Interrupt is inhibited. 1 (B_0x1): A SPDIFRX interface interrupt is generated whenever SBD = 1 in the SPDIFRX_SR register.
SYNCDIE	Synchronization done This bit is set and cleared by software. 0 (B_0x0): Interrupt is inhibited. 1 (B_0x1): A SPDIFRX interface interrupt is generated whenever SYNCD = 1 in the SPDIFRX_SR register.
IFEIE	Serial interface error interrupt enable This bit is set and cleared by software. 0 (B_0x0): Interrupt is inhibited. 1 (B_0x1): A SPDIFRX interface interrupt is generated whenever SERR = 1, TERR = 1, or FERR = 1 in the SPDIFRX_SR register.

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