stm32 /stm32h7rs /STM32H7R /TIM12 /TIM12_CCMR1_OUTPUT

Capture/Compare 1 selection This bitfield defines the direction of the channel (input/output) as well as the used input. Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

0 (B_0x0): CC1 channel is configured as output

1 (B_0x1): CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1

2 (B_0x2): CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2

3 (B_0x3): CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)

Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output.

0 (B_0x0): CC1 behaves normally depending on the counter and CCR1 values even when the trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the trigger input is 5 clock cycles

1 (B_0x1): An active edge on the trigger input acts like a compare match on the CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode.

Output compare 1 preload enable

0 (B_0x0): Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately

1 (B_0x1): Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded into the active register at each update event

OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal tim_oc1ref from which tim_oc1 is derived. tim_oc1ref is active high whereas the active level of tim_oc1 depends on the CC1P. Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode.

0 (B_0x0): Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

1 (B_0x1): Set channel 1 to active level on match. The tim_oc1ref signal is forced high when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).

2 (B_0x2): Set channel 1 to inactive level on match. The tim_oc1ref signal is forced low when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).

3 (B_0x3): Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1

4 (B_0x4): Force inactive level - tim_oc1ref is forced low

5 (B_0x5): Force active level - tim_oc1ref is forced high

6 (B_0x6): PWM mode 1 - channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else it is inactive

7 (B_0x7): PWM mode 2 - channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else it is active

Capture/Compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

0 (B_0x0): CC2 channel is configured as output

1 (B_0x1): CC2 channel is configured as input, IC2 is mapped on tim_ti2

2 (B_0x2): CC2 channel is configured as input, IC2 is mapped on tim_ti1

3 (B_0x3): CC2 channel is configured as input, IC2 is mapped on tim_trc. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register

Output compare 2 fast enable

Output compare 2 preload enable

OC2M[2:0]: Output compare 2 mode Refer to OC1M[3:0] for bit description.

OC1M[3]

OC2M[3]