UIFREMAP=B_0x0, UDIS=B_0x0, ARPE=B_0x0, DITHEN=B_0x0, OPM=B_0x0, URS=B_0x0, CKD=B_0x0, CEN=B_0x0
TIM12 control register 1
| CEN | Counter enable CEN is cleared automatically in one-pulse mode, when an update event occurs. Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 0 (B_0x0): Counter disabled 1 (B_0x1): Counter enabled |
| UDIS | Update disable This bit is set and cleared by software to enable/disable update event (UEV) generation. Counter overflow Setting the UG bit Buffered registers are then loaded with their preload values. 0 (B_0x0): UEV enabled. An UEV is generated by one of the following events: 1 (B_0x1): UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. |
| URS | Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow Setting the UG bit Update generation through the slave mode controller 0 (B_0x0): Any of the following events generates an update interrupt if enabled. These events can be: 1 (B_0x1): Only counter overflow generates an update interrupt if enabled. |
| OPM | One-pulse mode 0 (B_0x0): Counter is not stopped on the update event 1 (B_0x1): Counter stops counting on the next update event (clearing the CEN bit). |
| ARPE | Auto-reload preload enable 0 (B_0x0): TIMx_ARR register is not buffered. 1 (B_0x1): TIMx_ARR register is buffered. |
| CKD | Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and sampling clock used by the digital filters (tim_tix), 0 (B_0x0): tDTS = ttim_ker_ck 1 (B_0x1): tDTS = 2 ttim_ker_ck 2 (B_0x2): tDTS = 4 ttim_ker_ck |
| UIFREMAP | UIF status bit remapping 0 (B_0x0): No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1 (B_0x1): Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. |
| DITHEN | Dithering enable Note: The DITHEN bit can only be modified when CEN bit is reset. 0 (B_0x0): Dithering disabled 1 (B_0x1): Dithering enabled |