TG=B_0x0, CC1G=B_0x0, UG=B_0x0
TIM12 event generation register
| UG | Update generation This bit can be set by software, it is automatically cleared by hardware. 0 (B_0x0): No action 1 (B_0x1): Re-initializes the counter and generates an update of the registers. The prescaler counter is also cleared and the prescaler ratio is not affected. The counter is cleared. |
| CC1G | Capture/compare 1 generation This bit is set by software to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: the CC1IF flag is set, the corresponding interrupt is sent if enabled. If channel CC1 is configured as input: The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 0 (B_0x0): No action 1 (B_0x1): A capture/compare event is generated on channel 1: |
| CC2G | Capture/compare 2 generation refer to CC1G description |
| TG | Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0 (B_0x0): No action 1 (B_0x1): The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled |