DBL=B_0x0, DBA=B_0x0
TIM15 DMA control register
| DBA | DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIM15_DMAR address). DBA is defined as an offset starting from the address of the TIM15_CR1 register. Example: … 0 (B_0x0): TIM15_CR1, 1 (B_0x1): TIM15_CR2, 2 (B_0x2): TIM15_SMCR, |
| DBL | DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIM15_DMAR address). … 0 (B_0x0): 1 transfer, 1 (B_0x1): 2 transfers, 2 (B_0x2): 3 transfers, 17 (B_0x11): 18 transfers. |
| DBSS | DMA burst source selection This bitfield defines the interrupt source that triggers the DMA burst transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). Other: reserved 1 (B_0x1): Update 2 (B_0x2): CC1 3 (B_0x3): CC2 6 (B_0x6): COM 7 (B_0x7): Trigger |