MSM=B_0x0, SMS=B_0x0, TS=B_0x0
TIM9 slave mode control register
| SMS | SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode (including gated + reset mode) must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC,…) receiving the tim_trgo signals must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 0 (B_0x0): Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. 4 (B_0x4): Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. 5 (B_0x5): Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 6 (B_0x6): Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled. 7 (B_0x7): External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. |
| TS | TS[0]: Trigger selection This TS[4:0] bitfield selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 658: TIMx internal trigger connection for more details on the meaning of tim_itrx for each timer. Note: These bits must be changed only when they are not used (for example when SMS=000) to avoid wrong edge detections at the transition. 0 (B_0x0): Internal Trigger 0 (tim_itr0) 1 (B_0x1): Internal Trigger 1 (tim_itr1) 2 (B_0x2): Internal Trigger 2 (tim_itr2) 3 (B_0x3): Internal Trigger 3 (tim_itr3) 4 (B_0x4): tim_ti1 Edge Detector (tim_ti1f_ed) 5 (B_0x5): Filtered Timer Input 1 (tim_ti1fp1) 6 (B_0x6): Filtered Timer Input 2 (tim_ti2fp2) |
| MSM | Master/Slave mode 0 (B_0x0): No action 1 (B_0x1): The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful in order to synchronize several timers on a single external event. |
| SMS_1 | SMS[3] |
| TS_1 | TS[4:3] |