stm32 /stm32h7rs /STM32H7R /VREFBUF /VREFBUF_CSR

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Interpret as VREFBUF_CSR

ENVR=B_0x0, VRR=B_0x0, HIZ=B_0x0

Description

VREFBUF control and status register

Fields

ENVR	Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. 0 (B_0x0): Internal voltage reference mode disable (external voltage reference mode). 1 (B_0x1): Internal voltage reference mode (reference buffer enable or hold mode) enable.
HIZ	High impedance mode This bit controls the analog switch to connect or not the V_REF+ pin. Refer to Table 229: VREF buffer modes for the mode descriptions depending on ENVR bit configuration. 0 (B_0x0): V_REF+ pin is internally connected to the voltage reference buffer output. 1 (B_0x1): V_REF+ pin is high impedance.
VRR	Voltage reference buffer ready 0 (B_0x0): the voltage reference buffer output is not ready. 1 (B_0x1): the voltage reference buffer output reached the requested level.
VRS	Voltage reference scale These bits select the value generated by the voltage reference buffer. VRS = 000: VREFBUF0 voltage selected. VRS = 001: VREFBUF1 voltage selected. VRS = 010: VREFBUF2 voltage selected. VRS = 011: VREFBUF3 voltage selected. Others: Reserved Refer to the product datasheet for each VREFBUFx voltage setting value. Note: The software can program this bitfield only when the VREFBUF is disabled (ENVR=0).

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