SYNCPOL=B_0x0, SYNCSRC=B_0x0, SYNCDIV=B_0x0
CRS configuration register
| RELOAD | Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section 7.5.2 for more details about counter behavior. |
| FELIM | Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section 7.5.3 for more details about FECAP evaluation. |
| SYNCDIV | SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 0 (B_0x0): SYNC not divided (default) 1 (B_0x1): SYNC divided by 2 2 (B_0x2): SYNC divided by 4 3 (B_0x3): SYNC divided by 8 4 (B_0x4): SYNC divided by 16 5 (B_0x5): SYNC divided by 32 6 (B_0x6): SYNC divided by 64 7 (B_0x7): SYNC divided by 128 |
| SYNCSRC | SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE clock or the SYNC pin must be used as SYNC signal. 0 (B_0x0): CRS_SYNC pin selected as SYNC signal source 1 (B_0x1): LSE selected as SYNC signal source 2 (B_0x2): OTG HS SOF selected as SYNC signal source (default) 3 (B_0x3): FIELD Reserved |
| SYNCPOL | SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. 0 (B_0x0): SYNC active on rising edge (default) 1 (B_0x1): SYNC active on falling edge |