stm32 /stm32h7rs /STM32H7S /CRYP /CRYP_CR

Algorithm direction This bit selects the algorithm direction. Attempts to write the bitfield are ignored when BUSY is set.

0 (B_0x0): Encryption

1 (B_0x1): Decryption

ALGOMODE[2:0]: Algorithm mode This bitfield selects the AES algorithm/chaining mode. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set.

4 (B_0x4): Electronic codebook (ECB)

5 (B_0x5): Cipher Block Chaining (CBC)

6 (B_0x6): Counter mode (CTR)

7 (B_0x7): AES key preparation for ECB or CBC decryption

Data type This bitfield defines the format of data written in the CRYP_DINR register or read from the CRYP_DOUTR register, through selecting the mode of data swapping. This swapping is defined in Section 60.4.15: CRYP data registers and data swapping. Attempts to write the bitfield are ignored when BUSY is set.

0 (B_0x0): No swapping (32-bit data).

1 (B_0x1): Half-word swapping (16-bit data).

2 (B_0x2): Byte swapping (8-bit data).

3 (B_0x3): Bit-level swapping.

Key size selection This bitfield defines the key length in bits of the key used by CRYP. When KEYSIZE is changed, KEYVALID bit is cleared. Attempts to write the bitfield are ignored when BUSY is set.

0 (B_0x0): 128-bits

1 (B_0x1): 192 bits

2 (B_0x2): 256 bits

3 (B_0x3): FIELD Reserved

FIFO flush This bit enables/disables the flushing of CRYP input and output FIFOs. Reading this bit always returns 0. When CRYPEN is cleared, writing this bit to 1 flushes both input and output FIFOs (that is read and write pointers of the FIFOs are reset). FFLUSH bit must be set when BUSY is cleared, otherwise the FIFO is flushed, but the block being processed may be pushed into the output FIFO just after the flush operation, resulting in a non-empty FIFO condition. Attempts to write FFLUSH are ignored when CRYPEN is set.

0 (B_0x0): No effect

1 (B_0x1): FIFO flush enabled

CRYP enable This bit enables/disables the CRYP peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (ALGOMODE[3:0] at 0x7) and upon the completion of GCM/GMAC/CCM initialization phase. The bit cannot be set as long as KEYVALID is cleared.

0 (B_0x0): CRYP disabled

1 (B_0x1): CRYP enabled

GCM or CCM phase selection This bitfield selects the phase, applicable only with GCM, GMAC or CCM chaining modes. Attempts to write the bitfield are ignored when BUSY is set.

0 (B_0x0): Initialization phase

1 (B_0x1): Header phase

2 (B_0x2): Payload phase

3 (B_0x3): Final phase

ALGOMODE[3]

Number of padding bytes in last block This padding information must be filled by software before processing the last block of GCM payload encryption or CCM payload decryption, otherwise authentication tag computation is incorrect. … Attempts to write the bitfield are ignored when BUSY is set.

0 (B_0x0): All bytes are valid (no padding)

1 (B_0x1): Padding for the last LSB byte

15 (B_0xF): Padding for the 15 LSB bytes of last block.

Key mode selection This bitfield defines how the CRYP key can be used by the application. KEYSIZE must be correctly initialized when setting KMOD[1:0] different from zero. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set.

0 (B_0x0): Normal-key mode. Key registers are freely usable.

2 (B_0x2): Shared-key mode. If shared-key mode is properly initialized in SAES peripheral, the CRYP peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in CRYP key registers when BUSY bit is cleared and KEYVALID is set in the CRYP_SR register. Key error flag KERF is set otherwise in the CRYP_SR register.

CRYP peripheral software reset Setting the bit resets the CRYP peripheral, putting all registers to their default values, except the IPRST bit itself. This bit must be kept cleared while writing any configuration registers.