INIM=B_0x0, OUTIM=B_0x0
CRYP interrupt mask set/clear register
| INIM | Input FIFO service interrupt mask This bit enables or disables (masks) the CRYP input FIFO service interrupt generation when INRIS is set. 0 (B_0x0): Input FIFO interrupt is disabled (masked), masked interrupt status (INMIS) stays cleared 1 (B_0x1): Input FIFO interrupt is enabled (not masked) |
| OUTIM | Output FIFO service interrupt mask This bit enables or disables (masks) the CRYP output FIFO service interrupt generation when OUTRIS is set. 0 (B_0x0): Output FIFO interrupt is disabled (masked), masked interrupt status (OUTMIS) stays cleared 1 (B_0x1): Output FIFO interrupt is enabled (not masked) |