stm32 /stm32h7rs /STM32H7S /CRYP /CRYP_IV0LR

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Interpret as CRYP_IV0LR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IVI

Description

CRYP initialization vector register 0L

Fields

IVI

Initialization vector bit x This bitfield stores the initialization vector bits [127:96] for AES chaining modes other than ECB. The value stored in CRYP_IVxR/LR registers is updated by hardware after each computation round (when applicable). Write to this register is ignored when CRYP is busy (BUSY bit set).

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