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stm32 /stm32h7rs /STM32H7S /CRYP /CRYP_K0LR

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Interpret as CRYP_K0LR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0K

Description

CRYP key register 0L

Fields

K

Key bit x This write-only bitfield contains the bits [255:224] of the AES encryption or decryption key, depending on the operating mode. Write to CRYP_KxR/LR registers is ignored when CRYP is busy (BUSY bit set). When key is coming from the SAES peripheral (KMOD[1:0] = 0x2), write is also ignored. With KMOD[1:0] at 0x0, a special writing sequence is required. In this sequence, any valid write to CRYP_KxR/LR register clears the KEYVALID flag except for the sequence-completing write that sets it. Also refer to the description of the KEYVALID flag in the CRYP_SR register.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32