INMIS=B_0x0, OUTMIS=B_0x0
CRYP masked interrupt status register
| INMIS | Input FIFO service masked interrupt status This read-only bit is set by hardware when an input FIFO flag (IFNF or IFEM) is set in CRYP_SR register. If the INIM mask bit is cleared in CRYP_IMSCR register, the INMIS bit stays cleared (masked). The INMIS bit is cleared by writing data to the input FIFO until IFEM flag is cleared (there is at least one word in input FIFO), or by clearing CRYPEN, When CRYP is disabled, INMIS bit stays low even if the input FIFO is empty. 0 (B_0x0): No input FIFO event detected or INIM mask cleared in CRYP_IMSCR or CRYPEN bit cleared. 1 (B_0x1): Input FIFO empty or not full detected, with an interrupt pending |
| OUTMIS | Output FIFO service masked interrupt status This read-only bit is set by hardware when an output FIFO flag (OFFU or OFNE) is set in CRYP_SR register. If the OUTIM mask bit is cleared in CRYP_IMSCR register, the OUTMIS bit stays cleared (masked). The OUTMIS bit is cleared by reading data from the output FIFO until OFNE flag is cleared (output FIFO empty). It is not cleared by disabling CRYP with CRYPEN bit. 0 (B_0x0): No output FIFO event detected or OUTIM mask cleared in CRYP_IMSCR 1 (B_0x1): Output FIFO full or not empty detected, with an interrupt pending |