ADDSET=B_0x0, ADDHLD=B_0x0, ACCMOD=B_0x0, BUSTURN=B_0x0, DATAST=B_0x0
SRAM/NOR-flash write timing registers for bank 3
| ADDSET | Address setup phase duration. These bits are written by software to define the duration of the address setup phase in fmc_ker_ck cycles (refer to Figure 109 to Figure 121), used in asynchronous accesses: … Note: In synchronous accesses, this value is not used, the address setup phase is always 1 flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 (B_0x0): ADDSET phase duration = 0 fmc_ker_ck clock cycle 15 (B_0xF): ADDSET phase duration = 15 fmc_ker_ck clock cycles (default value after reset) |
| ADDHLD | Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 109 to Figure 121), used in asynchronous multiplexed accesses: … Note: In synchronous NOR flash accesses, this value is not used, the address hold phase is always 1 flash clock period duration. 0 (B_0x0): FIELD Reserved 1 (B_0x1): ADDHLD phase duration = 1 fmc_ker_ck clock cycle 2 (B_0x2): ADDHLD phase duration = 2 fmc_ker_ck clock cycle 15 (B_0xF): ADDHLD phase duration = 15 fmc_ker_ck clock cycles (default value after reset) |
| DATAST | Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 109 to Figure 121), used in asynchronous SRAM, PSRAM and NOR flash memory accesses: … 0 (B_0x0): FIELD Reserved 1 (B_0x1): DATAST phase duration = 1 fmc_ker_ck clock cycles 2 (B_0x2): DATAST phase duration = 2 fmc_ker_ck clock cycles 255 (B_0xFF): DATAST phase duration = 255 fmc_ker_ck clock cycles (default value after reset) |
| BUSTURN | Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) fmc_ker_ck period more or equal to tEHELmin. The programmed bus turnaround delay is inserted between an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different expect for muxed or mode D. In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed and D modes. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous writes (burst or single) to the same bank. A synchronous write (burst or single) transfer and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous writes (burst or single) to different static bank. A synchronous write (burst or single) transfer and a synchronous read from the same or a different bank. … 0 (B_0x0): BUSTURN phase duration = 0 fmc_ker_ck clock cycle added 15 (B_0xF): BUSTURN phase duration = 15 fmc_ker_ck clock cycles added (default value after reset) |
| ACCMOD | Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 0 (B_0x0): access mode A 1 (B_0x1): access mode B 2 (B_0x2): access mode C 3 (B_0x3): access mode D |