MODE=B_0x0, CTB2=B_0x0, NRFS=B_0x0, CTB1=B_0x0
SDRAM Command mode register
| MODE | Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0. 0 (B_0x0): Normal Mode 1 (B_0x1): Clock Configuration Enable 2 (B_0x2): PALL (All Bank Precharge) command 3 (B_0x3): Auto-refresh command 4 (B_0x4): Load Mode Register 5 (B_0x5): Self-refresh command 6 (B_0x6): Power-down command 7 (B_0x7): FIELD Reserved |
| CTB2 | Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not. 0 (B_0x0): Command not issued to SDRAM Bank 2 1 (B_0x1): Command issued to SDRAM Bank 2 |
| CTB1 | Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not. 0 (B_0x0): Command not issued to SDRAM Bank 1 1 (B_0x1): Command issued to SDRAM Bank 1 |
| NRFS | Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. … 0 (B_0x0): 1 Auto-refresh cycle 1 (B_0x1): 2 Auto-refresh cycles 14 (B_0xE): 15 Auto-refresh cycles 15 (B_0xF): 16 Auto-refresh cycles |
| MRD | Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD[13:0] bits are also used to program the extended mode register for mobile SDRAM. |