stm32 /stm32h7rs /STM32H7S /SAES /SAES_ISR

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Interpret as SAES_ISR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CCF 0 (B_0x0)RWEIF 0 (B_0x0)KEIF 0 (B_0x0)RNGEIF

CCF=B_0x0, RWEIF=B_0x0, KEIF=B_0x0, RNGEIF=B_0x0

Description

SAES interrupt status register

Fields

CCF

Computation complete flag This flag indicates whether the computation is completed: The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the SAES_IER register. The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.

0 (B_0x0): Not completed

1 (B_0x1): Completed

RWEIF

Read or write error interrupt flag This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the SAES_SR register. RWEIF bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the SAES_IER register. This flags has no meaning when key derivation mode is selected.

0 (B_0x0): No read or write error detected

1 (B_0x1): Read or write error detected (see SAES_SR register for details)

KEIF

Key error interrupt flag This read-only bit is set by hardware when key information failed to load into key registers or key register usage is forbidden. Setting the corresponding bit of the SAES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the SAES_IER register is set. KEIF is triggered upon any of the following errors: SAES fails to load the DHUK (KEYSEL = 001 or 100). SAES fails to load the BHK (KEYSEL = 010 or 100) respecting the correct order. SAES fails to load the AHK (KEYSEL = 011 or 101). CRYP fails to load the key shared by SAES peripheral (KMOD = 10). SAES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 register, or reverse. For KEYSIZE = 1, SAES_KEYR0 then SAES_KEYR1 then SAES_KEYR2 then SAES_KEYR3 then SAES_KEYR4 then SAES_KEYR5 then SAES_KEYR6 then SAES_KEYR7, or reverse). KEIF must be cleared by the application software, otherwise KEYVALID cannot be set.

0 (B_0x0): No key error detected

1 (B_0x1): Key information failed to load into key registers, or key register use is forbidden

RNGEIF

RNG error interrupt flag This read-only bit is set by hardware when an error is detected on RNG bus interface (e.g. bad entropy). RNGEIE bit is cleared when application sets the corresponding bit of SAES_ICR register. An interrupt is generated if the RNGEIE bit has been previously set in the SAES_IER register. Clearing this bit triggers the reload of a new random number from RNG peripheral.

0 (B_0x0): RNG bus is functional

1 (B_0x1): Error detected on RNG bus interface (random seed fetching error)

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